Junior Research Fellow (JRF) / Project Associate-I Recruitment 2026 at NIT Calicut – MeitY Sponsored VLSI Research Project
INR 30,000 - INR 37,000 per month + 18% HRA
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Junior Research Fellow (JRF) / Project Associate-I Recruitment 2026 at NIT Calicut – MeitY Sponsored VLSI Research Project
Position Overview
Particulars | Details |
|---|---|
Institution | National Institute of Technology Calicut (NIT Calicut) |
Office | Office of Research and Consultancy |
Department | Electronics and Communication Engineering |
Positions | Junior Research Fellow (JRF) / Project Associate-I (PA-I) |
Number of Positions | 02 |
Sponsoring Agency | Ministry of Electronics and Information Technology (MeitY) |
Project Title | High Precision Interfacing Circuit for Capacitive Based Sensors (HPICCS) |
Appointment Type | Contract Basis |
Initial Duration | 1 Year |
Extension | Extendable up to 2 years based on performance |
Age Limit | 35 Years |
Selection Mode | Online Interview |
Interview Date | October 6, 2026 |
Application Deadline | October 1, 2026 |
Location | NIT Calicut, Kerala |
About the Opportunity
The National Institute of Technology Calicut (NIT Calicut) invites applications for Junior Research Fellow / Project Associate-I positions under a research project in the Department of Electronics and Communication Engineering.
The project is sponsored by MeitY and focuses on the development of high-precision electronic interfacing circuits for capacitive-based sensors.
Project Title
“High Precision Interfacing Circuit for Capacitive Based Sensors (HPICCS)”
The project involves advanced work in VLSI, ASIC design, circuit design, physical design, and sensor-interface electronics.
Essential Qualification
Candidates should possess:
First Class B.Tech./B.E. in Electronics and Communication Engineering (ECE)
or
A closely allied discipline.
Desirable Qualification
Preference may be given to candidates having:
M.Tech. in VLSI or a related area
Knowledge or proficiency in schematic design
Experience with layout design
Familiarity with Cadence tools
Experience Required
No separate mandatory professional experience requirement is specified in the advertisement.
Candidates with relevant exposure to VLSI design, ASIC development, Cadence tools, circuit layout, and physical design will be well suited to the project.
Project Area
The project broadly focuses on:
VLSI Design
ASIC Design
Sensor Interface Circuits
Capacitive Sensors
Integrated Circuit Design
Physical Design
Schematic and Layout Design
Semiconductor Design
Area of Work
The selected candidates may contribute to:
ASIC design
Physical design
Circuit schematic development
Layout activities
Technical documentation
Tape-out related activities
Remuneration
Position 1: JRF / Project Associate-I
For GATE/NET qualified candidates:
JRF: INR 37,000 per month + 18% HRA
For candidates not meeting the JRF qualification condition:
Project Associate-I: INR 30,000 per month + 18% HRA
Position 2: Project Associate-I
INR 30,000 per month + 18% HRA
Appointment Duration
The appointment will initially be for:
1 Year
It may be extended up to 2 years, depending on:
Candidate performance
Project requirements
The engagement is purely on a contract basis.
Age Limit
Maximum Age: 35 years
Age relaxation will be applicable as per Government of India norms.
Nature of Appointment
Contractual research position
MeitY-sponsored project
Department of Electronics and Communication Engineering
Initial tenure of 1 year
Extendable based on performance
How to Apply
Eligible candidates should submit their applications according to the procedure prescribed by the Office of Research and Consultancy, NIT Calicut.
The detailed application link / submission instructions are not visible in the provided advertisement excerpt.
Important Dates
Event | Date |
|---|---|
Last Date for Application Submission | October 1, 2026 |
Online Interview | October 6, 2026 |
Job Domain: Engineering and Technology / Electronics & Communication Engineering / VLSI / ASIC Design / Semiconductor Technology
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